Mixed technologies on a single wafer can present challenges. Certain technologies have higher performance and corresponding higher leakage power while other technologies have lower performance and corresponding lower leakage power. When designing the layout of certain logic circuits, the conventional design strategy is to not allow an overlap of cell layouts for cells of different technologies or to allow some overlap at the risk of creating complexity and issues that affects the functionality of the overall integrated circuits used on a single wafer. Such design layout strategies ultimately fail to provide for a device having both high performance (such as high switching speed) and low leakage current.
The overlap designs having mixed technologies are haphazard and only tend to confuse the operational function of the devices in the design. As design sizes become smaller and smaller and the drive for higher density devices increases, the greater the potential problems in mixing and overlapping different cell technologies on a single wafer.